AVR Jtag ICE enables AVR based ICs to be debugged using hardware breakpoints.
The JTAG interface is a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE 1149.1 standard. The IEEE standard was developed to enable a standard way to efficiently test circuit board connectivity (Boundary Scan). Atmel AVR devices have extended this functionality to include full Programming and On-chip Debugging support.
The JTAG ICE uses the standard JTAG interface to enable the user to do real-time emulation of the microcontroller while it is running in the target system.
- AVR Studio ver-4 and IAR Embedded WorkBench Compatible
- Supports AVR Devices with JTAG Interface(see the supported devices session for compatibility)
- Break on Change of Program Flow
- Data and Program Memory Breakpoints
- Supports Assembler and HLL Source Level Debugging
- USB Interface to PC for Programming and Control