Elementz AVR Jtag ICE for AVR hardware debugging

AVR Jtag ICE enables AVR based ICs to be debugged using hardware breakpoints.

jtag_snap

The JTAG interface is a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE 1149.1 standard. The IEEE standard was developed to enable a standard way to efficiently test circuit board connectivity (Boundary Scan). Atmel AVR devices have extended this functionality to include full Programming and On-chip Debugging support.

The JTAG ICE uses the standard JTAG interface to enable the user to do real-time emulation of the microcontroller while it is running in the target system.

Features

  • AVR Studio ver-4 and IAR Embedded WorkBench Compatible
  • Supports AVR Devices with JTAG Interface(see the supported devices session for compatibility)
  • Break on Change of Program Flow
  • Data and Program Memory Breakpoints
  • Supports Assembler and HLL Source Level Debugging
  • USB Interface to PC for Programming and Control

Wiki Page: http://elementzonline.com/wiki/Elementz_AVR_JTAG_V1.1

UserManual: https://github.com/elementzonline/AVR_JtagProgrammer

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